1. Field of the Invention
The present invention relates to a cell of a cache memory array, currently designated in the art as a CAM (Content Addressed Memory), and more specifically to such a cell provided with a masking element.
2. Discussion of the Related Art
FIG. 1 shows a conventional CAM cell above dash and dot line 1. This cell is associated with two complementary bit lines BL1 and {overscore (BL1)}, shown vertically, with a word line WL1 shown horizontally, and with a result line {overscore (MATCH)} shown horizontally. The bit lines are common to cell columns, and the word and result lines are common to cell rows.
The CAM cell includes a storage element and a comparison element.
The storage element includes, between lines BL1 and {overscore (BL1)}, the series connection of a MOS transistor T1, of two anti-parallel inverters INV1 and INV2, and of a MOS transistor T2. The gates of transistors T1 and T2 are connected to word line WL1. To store a state, a 1 is placed on word line WL1. Both transistors T1 and T2 are then on and points ST and {overscore (ST)} located on either side of the inverters take, respectively, the states existing on lines BL1 and {overscore (BL1)}. Word line WL1 is then reset to zero, transistors T1 and T2 are turned off and the state of points ST and {overscore (ST)} is stored.
The comparison element includes two MOS transistors NB and NA in series between lines BL1 and {overscore (BL1)}. Connection point CMP of these two transistors is connected to the gate of a transistor NC connected between a result line {overscore (MATCH)} and the ground. In a comparison step, line WL1 is maintained at zero and lines BL1 and {overscore (BL1)} are set to the state which is desired to be compared to the previously stored state. It can be seen that, if the stored state is reproduced on lines BL1 and {overscore (BL1)}, point CMP is at a low level (0) and transistor NC is off. The state of result line {overscore (MATCH)} (which is maintained at a high voltage Vdd by a resistor or any other means for setting to the high state) is thus not modified. In fact, since line {overscore (MATCH)} is connected to all the cells in a same row, it is thus checked whether a word to be compared is identical or not to a preceding word. However, if a bit of a word to be compared differs from the corresponding bit of the stored word, point CMP of the corresponding cell switches high, the corresponding transistor NC turns on and line {overscore (MATCH)} changes state and switches to zero.
FIG. 1 shows, under a compound line 1, circuit elements enabling inhibition (“masking”) of a cell. Indeed, it is desired to be able to compare words, some bits of which are indifferent. To achieve this result, an additional transistor ND is provided between transistor NC and the ground. Transistor ND is made permanently conductive when the comparison of the involved cell is effectively desired to be validated and is permanently blocked when the comparison is desired to be inhibited. Indeed, in this latter case, whatever the state of transistor NC, the ground connection of result line {overscore (MATCH)} for the involved cell is permanently open. To control transistor ND, a storage cell including transistors T3 and T4 and inverters INV3 and INV4, similar to the components of the previously-described storage element of the CAM cell but arranged between bit lines BL2 and {overscore (BL2)} and associated with a word line WL2, is provided.
As shown in FIG. 2, an inverter includes two complementary MOS transistors in series between a high voltage source VDD and ground GND, input E of the inverter corresponding to the common gates of these transistors and output S of the inverter corresponding to the common terminal of the two transistors. Thus, the circuit of FIG. 1 includes 16 MOS transistors: 12 N-channel transistors and 4 P-channel transistors.
FIG. 3 very schematically illustrates the shape of an elementary MOS transistor. This transistor includes, on either side of a gate G, heavily-doped source and drain regions of a first conductivity type, formed in a substrate of the opposite conductivity type. The active areas are separated from one another by thick oxide regions (SiO2). The transistor of FIG. 3 is an N-channel transistor. The P-channel transistors have a similar structure, all conductivity types being inverted. This means that they are formed in an N-type substrate or well. The N wells in which the P-channel transistors are formed must be at a non-negligible distance from the limit of the closest N-type transistors. This leads to gathering all the P-type transistors in a common well.
FIG. 4 shows in top view an example of implementation in the form of an integrated circuit of the circuit of FIG. 1. All the P-type transistors, that is, the P-type transistors of inverters INV1 to INV4, are gathered in a same well 10.
FIG. 4 is extremely simplified. The active areas of the transistors are shown as white rectangles. The polysilicon layers that form gates at the locations where they cut the active areas are hatched. The reference of each transistor is shown at the location where the gate of this transistor covers its active area. The areas of contact with the various regions are marked with a cross. The connections between transistor terminals, when not ensured by an extension of an active area, are indicated by dotted lines. In practice, these connections will be ensured by one or the other of various metallization levels formed on the integrated circuit. The two transistors of a same inverter INV are designated by a same reference I. For example, the N-channel and P-channel transistors of inverter INV2 are both designated by reference I2, it being understood that the transistor designated by reference I2 arranged in well 10 is a P-channel transistor and that the transistor designated by reference I2 external to well 10 is an N-channel transistor.
As illustrated in FIG. 4, transistors T1 and T2, N-channel transistors I1 and I2 of inverters INV1 and INV2, and transistors NA and NB are arranged at the top of the drawing, above well 10. Transistors NC and ND, N-channel transistors I3 and I4 of inverters INV3, INV4, and transistors T3 and T4 are arranged at the bottom of the drawing, under well 10. This arrangement corresponds to an optimization of the circuit resulting from many improvements performed by specialized designers.
Experience shows that, for example in a line such as line HCMOS8 of STMicroelectronics, in which the minimum dimension of a pattern is 0.18 μm, a structure having a 23.5-μm2 surface area is obtained. With a line of type HCMOS9 in which the minimum dimension of a pattern is 0.12 μm, a 12-μm2 surface area is obtained. Such surface areas are not compressible due to the minimum guard distances to be maintained between the different components and the metallizations connecting them. It should in particular be noted that one of the factors that take a great part in the surface area of an integrated circuit results from the provision of connection areas or connection pads from which vias will be grown and on which it will be possible to perform a connection with metallizations.